1. Field of the Invention
This invention relates to a semiconductor memory device having a stack-type capacitor, for example, and more particularly to a semiconductor memory device obtained by improving the wiring layer of a dynamic random access memory (DRAM).
2. Description of the Related Art
In recent years, the integration density of the DRAM has been enhanced and the area of a capacitor for storing data or information (charges) has been further reduced accordingly. As a result, problems that the memory data is erroneously read out or a soft error is caused by .alpha.-rays to destroy the memory data may occur.
As a method of solving the above problems and attaining the high integration density and large capacity, the following method is proposed. AMOS capacitor is formed on a memory cell area, and one of the electrodes of the capacitor is electrically connected to one electrode of a switching transistor formed on the semiconductor substrate. A memory cell with the above structure is usually called a stack-type memory cell, the occupied area of the capacitor is substantially increased and the electrostatic capacity of the MOS capacitor is increased.
In the memory cell with the above structure, the storage node electrode can be formed to extend over the element separating region and the side wall of the storage node electrode can be used as a capacitor by increasing the film thickness of the storage node electrode so that the capacity thereof can be made several times larger than that of the planar structure. Further, since the diffusion layer of the storage node section includes only a diffusion region below the storage node electrode, the area of the diffusion layer for collecting charges generated by .alpha.-rays is extremely small and the cell structure which is highly resistive to the soft error can be obtained.
With the above structure, since the capacity of the DRAM larger than 64 Mbits becomes insufficient, a cylindrical type structure for increasing the capacitance of the capacitor by use of the side wall of the storage electrode and a storage electrode structure of fin-type structure having a storage electrode formed in a multi-layered form are proposed.
However, with the above storage electrode structure, the height of the storage electrode becomes large (500 to 1000 nm), and in the peripheral circuit section, there occurs a problem that wiring from the first Al wire to the lower layer or the contact to the substrate is deep and connection becomes difficult.
As described above, in the conventional stack-type DRAM, when it is desired to attain a sufficiently large storage capacity, the height of the storage node becomes large, an insulation film for planarization becomes thick and the contact hole becomes deep, thereby making it difficult to make connection with the substrate.